Recent trends in processor architecture design often involve adding more processor cores on a given integrated circuit (IC), and enabling more threads per core. This trend has driven the demand for on-chip secondary cache memory, often referred to as Level-2 (L2) cache. As the aggregate processing power of an IC grows, the capacity of the corresponding cache memories must grow accordingly. Hence, there is a renewed demand for very dense (e.g., about one gigabit (Gb) or higher) on-chip storage. While dynamic storage (e.g., dynamic random access memory (DRAM), gain-cells, etc.) provides one of the most dense memory architectures, dynamic storage generally requires periodic refreshing since, over time, finite leakage associated with dynamic memory cells can add or remove enough charge so that it can disturb the respective states of the memory cells.
Variations in certain characteristics of dynamic memory cells (e.g., data retention time, temperature dependence, etc.) generally do not correlate with one another. Thus, the rate at which refreshing occurs in the overall memory is typically based on a worst-case statistical analysis, which often represents an overburden to the processor system. Moreover, after a read operation is performed, the contents of a dynamic memory cell must be restored because the sensing required to detect the state of the memory cell also destroys its contents. Periodic refresh actions also undesirably stall other pending processor requests, thereby reducing memory and/or processing bandwidth. Some of the historical notions relating to dynamic storage, however, are derived from the use of dynamic memory in a persistent memory (e.g., main memory) environment, and may be irrelevant in the context of a cache memory application.
U.S. Pat. No. 6,389,505 issued to P. Emma et al. on May 14, 2002 (hereinafter referred to as “Emma”), the disclosure of which is incorporated by reference herein, challenges the notion that all dynamic memory cells must be periodically refreshed. The Emma patent describes specific techniques which can enable DRAM to be used as cache memory by providing a restore tracking system for reducing the number of refresh actions needed to maintain data in the DRAM. In essence, data in dynamic storage can be left to “expire” in the context of a cache architecture. For example, since DRAM has a destructive read which is generally followed by a restore cycle, the only data that needs to be refreshed is data that has not been referenced in a relatively long period of time (e.g., greater than a retention time of the dynamic memory cell). Data that has not been referenced in a cache is usually considered “dead,” and therefore it need not be refreshed if it can be shown that the data contained therein is not likely to be used again (see, e.g., Zhigang Hu et al., “Let Caches Decay: Reducing Leakage Energy via Exploitation of Cache Generational Behavior,” ACM Transactions on Computer Systems (TOCS), May 2002, which is incorporated by reference herein). One disadvantage with this approach, however, is that it requires substantial overhead to administer the restore tracking system so that the system is a priori aware of the fact that certain data in the dynamic memory cells might be erroneous, and to ensure that such data is not inadvertently used.
There exists a need, therefore, for a dynamic memory architecture suitable for use in a cache memory system which does not suffer from one or more of the above-noted deficiencies associated with conventional dynamic storage and/or cache memory architectures.